High Definition
CMOS imagers are breaking technical barriers in noise, sensitivity and dynamic
range. They are even surpassing the
performance characteristics of CCD’s in many photonic, imaging and consumer
applications. By utilizing a single highly integrated CMOS device, which
incorporate Megapixel sensing areas, timing generation, signal processing and
high bandwidth outputs, a compact and low power high definition digital camera
operating at 30fps can be created. For
HDTV applications, the aspect ratio can be switched from the traditional 4:3 to
16:9 by utilizing a region-of-interest (ROI) readout A reduced size ROI enables readout rates in excess of
400 frames per second, ideal for motion analysis or tracking. For increased frame rate or film resolution Megapixel
systems, multiple regions of the sensor can be readout in parallel.
Converting the pixel data directly to digital at the CMOS sensor head
eliminates pixel-sampling jitter and enables accurate sub-pixel metrology, image
analysis or improved live video reconstruction.
For 10 to 12 bit per pixel resolution or multi-tap systems the number of
parallel digital signals becomes cumbersome to cable and physically large to
connect. This is most apparent in
micro remote-head cameras where the package size is critical to be suitable for
use in medical imaging systems, such as endoscopes, or robotic machine vision
systems. Therefore, high Speed
digital multiplexers are used to serialize the image data and transmit the
1.2~2.4Gb/sec data, clock and triggers over just a few twisted pairs, thereby
minimizing the cable size and increased flexibility.
The advent of
these new generation high definition Megapixel imagers has created a gap in the
market for silicon solutions, which can process this increased resolution data
at video rates and to produce image quality typical of 3-CCD cameras.
Most processors are optimized to produce 720x480 digital CCIR.BT.601
compliant video from a CCD with a 768x494 array.
Digital Still Camera (DSC) processors can support over 4 Megapixel arrays
but do not produce professional quality video and cannot stream the full
resolution images to a digital output at video rates. Utilizing the latest in VHDL tools and platform FPGA
architecture, the VADAR Processorä
(Video Acquisition, Detection, Arithmetic processing and Recognition)
intellectual property (IP) core has been developed to produce real-time high
definition digital video or perform complex image processing and communication,
as an alternative to costly custom ASIC solutions.
The VADAR
Processorä
core supports single or multi-sensor input configurations, which are beneficial
in stereo or multispectral imaging. Large
input FIFO memories and dedicated multiplier blocks implement color conversions,
image enhancement and wavelet convolution filters. A wide external SDRAM
and Double Data Rate (DDR) memory controller is incorporated for frame sequence
buffering, inter-image processing,
scaling, electronic Pan/Tilt, frame rate conversion and dual independent
time-base digital outputs. The
first output port is used to feed an external encoder to produce video for
display on computer XGA, DVI LCD, HDTV or traditional NTSC at resolutions up to
1920 x 1080i. The second output is initially
configured for USB 2.0 running at 480Mb/sec and CameraLink at 1.9Gb/sec
for Frame grabber connectivity.
However, using the programmability of the architecture, it is quickly
adapted to other high speed digital interface standards including IEEE
1394b (“Firewire”), broadcast SMPTE 292M 1.485Gb/s
Serial Digital Interface (SDI), Parallel LVDS or Ethernet to meet the diverse
range of Megapixel Imaging and communication requirements.
Keywords:
CMOS camera, HDTV, Medical Video Endoscope, 1394B, USB2.0, Megapixel, wavelet, SDI, USB2.0.